Computer architecture research involves heavy use of simulators, most of these simulators are cycle-approximate simulators (CAS) implemented using imperative (C), object oriented (C++) and multi-paradigm (Python) languages. Some of the widely used simulators are Gem5, GPGPU-Sim and McPAT.
In an ideal case, in computer architecture one would like to work with languages that are easy on the construction of synthesizable register-transfer-level and close to hardware design. Hardware Description languages (HDL) come under this category, which are heavily used in VLSI research and in industry, but not in computer architecture research. SystemVerilog, Verilog or VHDL are examples of these.
Prof. Christopher Batten and his group at Cornell University, put forward the idea of bringing together CAS and HDL in research paper “Hardware Generation Languages as a Foundation for Credible, Reproducible, and Productive Research Methodologies.” This paper brings together CAS and HDL to put forward the need of hardware generation languages (HGL) and integrated frameworks to improve researcher productivity in computer architecture.
I agree with the idea, as I have experienced the difference while working with CAS and HDL research methodologies, and how useful integrating these two could be. There are few HGL which have found their way into academia, namely Genesis2, Chisel and Bluespec. Chisel might find quick adaption due to its use with RISC-V, where as Bluespec and Genesis2 have been around for a while but not many research group are using it for computer architecture research. Prof. Christopher’s group is working on a Python framework that will bridge CAS and HDL, and that could be very useful considering that not all research is carried out using both the methodologies.
You can learn more about HGL languages by reading:
- Chisel: Constructing Hardware in a Scala Embedded Language
- Genesis2: A chip generator
- Bluespec System Verilog: efficient, correct RTL from high level specifications