Open ISA: The RISC-V

There has always been a debate over which instruction set architecture (ISA) is better, RISC or CISC. The research led by Prof. Krste Asanović and Prof. David A. Patterson at University of California, Berkeley (UCB) takes radical approach towards ISA. They have come up with an Open ISA called RISC-V. It might remind you of SPARC and OpenRISC, however this open ISA is very different in terms of features.


( Image Courtesy: Instruction Sets Should Be Free: The Case For RISC-V )

RISC-V is also backed up with excellent set of tools, that help early adopters in quick evaluation. This is very important considering that the last big open ISA project is still available, but since was never backed up with proper set of tools, makes it difficult to explore. My own experience of synthesizing single core of UltraSPARC T1 ended in disappointment. The tools used then were propitiatory, with RISC-V built on top of other open projects like Chisel open-source hardware construction language, will surely help quick adoption in the academia and later on in industry.

UCB is also conducting a workshop to demonstrate the capabilities of the RISC-V ISA. Today, the group was also part of an online podcast conducted by EE Times.

One more crucial thing being implemented in parallel to ISA development, is the development board called lowRISC. lowRISC is producing fully open hardware systems with SoC (System-on-a-Chip) designs which will make use of RISC-V. This is be very useful as it will push development of large code base, that might later merge with mainline Linux Kernel.

If you are interested to learn more about RISC-V, then I suggest reading:

Hi, I’m Chetan Arvind Patil, I write this blog